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0.6µm CMOS Analog Mixed Mode

Process Outline

  • 0.6µm P-Sub 1P3M(1-Poly and 3-Metal) Twin Well CMOS generic process.
  • Maximum operational voltage is 6V and maximum rating is 6.5V.
  • Transistor Characterizations are as follows;
DeviceTr.typeVth[V] *1Ids[uA/um]Ioff[pA/um]
PMOSLogic Tr.-0.952240.05
Low Tr.-0.601600.3
Analog Tr.-0.801640.2
NMOSLogic Tr.0.754600.1
Low Tr.0.3529630
Analog Tr.0.602640.2
  • *1Extrapolated Threshold at Vd=0.1V
  • Vth tunable to match customer's needs.

Option Modules

  • Depletion Transistor.
  • 20V and 40V Transistors.
  • Vertical PNP and Lateral PNP Transistors.
  • Triple well.
  • 0.5k , 1k , 2k and 10k-ohm/sq High Resistivity Poly Resistor. (* Tunable high resistivity poly to match customer's needs.)
  • Thin Film Resistor.
  • Low temperature coefficient Poly Resistor.
  • Double Poly Capacitor (PiP).
  • Laser Trimming Fuse.

Design Environment

  • BSIM3V3 based on analog oriented extraction is used for SPICE simulation.
  • SPICE parameters are ready for HSPICE, SPECTRE and Smart SPICE.
  • Characterization report is available.
  • Logic libraries and I/O libraries are available.
  • ESD protection circuit is available.

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