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0.35µm CMOS Analog Mixed Mode
Process Outline
- 0.35µm P-Sub 3P3M(3-Poly and 3-Metal) Twin Well CMOS generic process.
- Transistor Characterizations are as follows;
| Device | Tr.type | Vth[V] *1 | Ids[uA/um] | Ioff[pA/um] |
|---|---|---|---|---|
| PMOS | 6V Tr. | -0.65 | 332 | 0.3 |
| 4V Tr. | -0.80 | 264 | 0.2 | |
| 3V Tr. | -0.77 | 242 | 0.1 | |
| NMOS | 6V Tr. | 0.64 | 544 | 0.1 |
| 4V Tr. | 0.63 | 508 | 0.2 | |
| 3V Tr. | 0.65 | 504 | 0.1 |
- *1Extrapolated Threshold at Vd=0.1V
- Vth tunable for customers' needs.
Option Modules
- Depletion Transistor.
- 15V Transistor and Drain 20V/Gate 6V Transistor.
- Vertical PNP Transistor.
- Triple well.
- 0.4k and 3.5k-ohm/sq High Resistivity Poly Resister. (* Tunable high resistivity poly to match customer's needs.)
- Low temperature coefficient Poly Resistor.
- Double Poly Capacitor (PiP).
- Laser Trimming Fuse.
Design Environment
- BSIM3V3 based on analog oriented extraction is used for SPICE simulation.
- SPICE parameters are ready for HSPICE, SPECTRE and Smart SPICE.
- Characterization report is available.
- Logic libraries and I/O libraries are available.
- ESD protection circuit is available.
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